1. Field of the Invention
The present invention relates in general to computer buses and more particularly to a method for testing a computer bus using a bridge chip having a freeze-on-error option that permits a central processing unit (CPU) to recover and continue processing even when there is an error within the bus.
2. Related Art
Computer buses are an integral and vital part of a computer system that provide a path by which data travels within the computer system. Typically, the computer bus is a collection of wires that connects one part of the computer with another. For example, an internal bus connects internal computer components to a central processing unit (CPU) and main memory, while an expansion bus connects expansion boards (also called adapters) to the CPU and main memory. A computer bus includes a data bus, which transfers the data, and an address bus, which transfers information regarding where the data should go. The expansion bus includes a bus slot whereby an expansion board (or adapter) may be inserted to give the computer added capabilities. The expansion board is a printed circuit board such as, for example, a video adapter, graphics accelerator, sound card, accelerator board and an internal modem.
One popular type of computer bus is the local bus architecture. Local bus architecture includes both the Industry Standard Architecture (ISA) expansion bus and the Peripheral Component Interconnect (PCI) local bus. In general, the PCI local bus is a newer architecture than the ISA architecture and provides fast throughput that allows data to be exchanged rapidly by connecting directly or nearly directly to the CPU. One way of connecting the local bus architecture to the CPU is by using a bridge chip. A bridge chip is an integrated circuit that connects, for example, an expansion board within a PCI slot directly to the CPU of the computer. This brings the expansion board closer to the CPU in terms of data transfer and increases system performance.
An optional feature that is available on some bridge chips is a freeze-on-error option. Generally, the freeze-on-error option is on a PCI-to-PCI bridge chip and enables the CPU of the computer system to continue processing (and prevent computer system freezing, lock-up or shutdown) even when there is an error within the computer bus or an expansion board within a bus slot. When an error is detected the PCI-to-PCI bridge chip having the freeze-on-error option enabled freezes the expansion board""s PCI bus slot thereby halting the expansion board""s processing. This is a large advancement over previous bridge chips that froze the entire computer bus when an error occurred within one of the bus slots, forcing the entire computer system to halt processing and stop working. Thus, a PCI-to-PCI bridge chip having an enabled freeze-on-error option permits the CPU of a computer system to continue processing even when an error has occurred within a computer bus slot or expansion board.
Accordingly, what is needed is a method of testing a computer bus using a bridge chip having a freeze-on-error option in such a way as to assure proper functionality (such as, for example, error recovery capabilities) of the computer bus (including the bus slots). What is also needed is a method of testing the computer bus that takes advantage of the freeze-on-error option and tests the computer bus and bus slots without causing the computer system to freeze or stop working. Moreover, what is needed is a method for testing that is preferably transparent to a user such that the method does not require the user to perform any special procedure (such as restarting the computer system).
To overcome the limitations in the prior art as described above and other limitations that will become apparent upon reading and understanding the present specification, the present invention includes a method for a testing a computer bus using a bridge chip having a freeze-on-error option that permits the central processing unit (CPU,) to recover and continue processing even when there is an error within the bus. The present invention provides a method of testing the computer bus by conducting a test that remains transparent to a user and can be accomplished while performing standard diagnostics tests. In particular, the present invention injects an error into a specific bus slot of the computer bus to test the functionality of the computer bus. The present invention then recovers from the injected error condition without having the computer system shutdown or stop working and without having to restart the computer system.
The present invention is especially useful in checking the error recovery capabilities of a computer bus. The testing method of the present invention takes advantage of the bridge chip""s freeze-on-error option in order to test the computer bus without causing the computer system to stop operating. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip and injecting an error into the bus slot. The status of the bus slot with the injected error condition is determined, and the bus slot recovers from the injected error condition. Again the status of the bus slot without the injected error condition is determined. The error recovery capabilities of the computer bus are determined by examining the status of the bus slot both with the injected error condition and without the injected error condition.